Back-Gated CMOS on SOIAS For Dynamic Threshold Voltage Control

The simultaneous reduction of power supply and threshold voltages for low-power design without suffering performance losses will eventually reach the limit of diminishing returns as static leakage power dissipation becomes a significant portion of the total power consumption. This is especially acute in systems that are idling most of the time. In order to meet the opposing requirements of high performance at reduced power supply voltage and low-static leakage power during idle periods, a dynamic threshold voltage control scheme is proposed. A novel Silicon-On-Insulator (SOI)-based technology called Silicon-OnInsulator-with-Active-Substrate (SOIAS) was developed whereby a back-gate is used to control the threshold voltage of the frontgate; this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators. For a 250 mV switch in threshold voltage, a reduction of 3–4 decades in subthreshold leakage current was measured. I. THE SOIAS CONCEPT THE CONCEPT of the Silicon-On-Insulator-with-ActiveSubstrate (SOIAS) technology can be taken to many levels of complexity. The fundamental idea behind this technology is to add one or more conductive under layers beneath the buried oxide of a Silicon-On-Insulator (SOI) structure. Such layers can serve as buried interconnects, gates or both. To take this idea even further, one can imagine stacked SOI structures with embedded interconnects and gates in between them. The fabrication of SOIAS structures leverages off from many of the technologies developed for bulk and SOI CMOS processes (e.g., CMP and wafer bonding). There are several options and various degrees in which the buried layer or layers can be rendered conductive. On one extreme, the buried layer can be a refractory metal such as tungsten, or silicides of such metals which can withstand subsequent hightemperature processing. In this case, the buried conductive layer must be pre-patterned prior to bonding which can make the bonding process more challenging. On the other extreme, a blanket insulating/semi-insulating layer (e.g., intrinsic amorphous/polycrystalline silicon) can be used, and selective areas of the buried layer can be made conductive by ion implantation with dopants. This work focuses on the development of the latter approach with one buried layer of intrinsic polysilicon for the purpose of dynamic threshold voltage control in lowpower applications. Manuscript received June 3, 1996; revised January 6, 1997. The review of this paper was arranged by Editor G. W. Neudeck. This work was supported by the MIT Lincoln Laboratory. The work of I. Yang was supported by AT&T through a graduate fellowship. The authors are with the Department Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139 USA. Publisher Item Identifier S 0018-9383(97)03008-6. II. DYNAMIC THRESHOLD VOLTAGE CONTROL CONCEPT Many system computations are either temporally or spatially localized. Systems that are frequently idle, i.e., doing computation only for a small fraction of the time, operate in burstmode, and hence exhibit temporal locality. On the other side of the spectrum are systems that operate in continuous mode (e.g., active all of the time), and hence do not exhibit temporal locality. At the same time, a system may only have a fraction of its functional modules active all of the time; such systems exhibit spatial locality. This idea can be applied to lower levels of the hierarchy such as at the logic gate level or the transistor level. A global strategy for achieving high performance and low power in continuously computing systems (e.g., modules of a video compression system) has been the simultaneous reduction of supply voltage and threshold voltage where the optimal and are found for minimum total system energy by trading off dynamic energy for static leakage energy [1]–[3]. CMOS-based high-performance burst-mode computation systems (e.g., a microprocessor running an Xserver or cellular phone which is idling more than 90% of the time) will suffer high-static leakage energy dissipation operating at low with constant low even with clocks stopped. For example, even when a user is continuously entering data at the keyboard, the X-server is active, (i.e., doing computation), only 2–3% of the time [4]. In order to simultaneously achieve high performance during active periods and low leakage power during idle periods for burstmode computational systems, several schemes of reducing the leakage current have been proposed. The multiple CMOS design involves using high transistors to gate the low blocks [5], [6]. Both NMOS and PMOS transistors are needed in order to preserve state. These devices must be made large due to the finite resistance of these transistors. This will incur additional switching energy to switch these devices. Therefore, appropriate sizing of the high transistors is crucial. Another approach is the dynamic control of by biasing the bulkCMOS wells [7]. A triple well technology is required for this scheme. Furthermore, well biasing is complicated by the Nwell to P-well junction leakage current as well as source/drain to well junction leakage currents. Both of the above schemes are implemented at the functional module level; for example, in the well biasing scheme, all the transistors in the functional module have the same variable which is dependent on the well bias. The aforementioned technologies have been mainly proposed for implementation in bulk silicon CMOS. However, the maturity of the SOI technology in the past few years cannot be 0018–9383/97$10.00  1997 IEEE YANG et al.: BACK-GATED CMOS ON SOIAS 823 Fig. 1. SOIAS preparation using bonded SIMOX process. ignored, especially with the dramatic improvements in material quality. There are two modes of operation for SOI MOSFET’s: 1) fully depleted (FD) and 2) partially depleted (PD) channel region (body). In the conventional strongly FD SOI device, the silicon film thickness is usually less than or equal to half of the depletion width of the bulk device. The surface potentials at the front and back interfaces are strongly coupled to each other and capacitively coupled to the front-gate and the substrate through the front-gate oxide and buried oxide, respectively. Therefore, the potential throughout the silicon film, and hence the charge, is determined by the bias conditions on both the front-gate and the substrate. By replacing the substrate with a back-gate, the device becomes a dual-gated device. The FD design is unique to SOI because the front-gate and back-gate both have control of the charge in the silicon film. In the strongly PD SOI, the back-gate or substrate has no influence on the front surface potential. In the middle regime, the device is nominally PD and can become FD by applying a back-gate bias, thus, coupling of the front and back surface potentials still occurs. There have been numerous studies on the merits of fully depleted SOI CMOS and its implications for low-power electronics. Various researchers have exploited the use of FD SOI in dualgated devices in which the top and bottom gates are tied and switched together, resulting in enhanced transconductance [8]–[11]. The SOIAS technology was developed to fabricate back-gated FD CMOS devices by capitalizing on existing SIMOX, wafer bonding, and thinning technologies [12]. The back-gate controls the of the front-gate device, and the NMOS and PMOS back-gates are switched independently from each other and the front-gates. For burst-mode highperformance and low-power applications, the threshold voltage would be raised during idle periods to reduce the static leakage current, and lowered during active periods to achieve high performance. Similar to the well biasing scheme, the SOIAS technology is proposed to be implemented at the functional module level. This paper describes the development of the SOIAS technology with implementation in a selectively scaled CMOS SOI baseline process, and a theoretical evaluation for low-power logic applications. III. SOIAS PREPARATION AND MATERIAL CHARACTERIZATION The SOIAS substrate is a multilayered blanket film stack consisting of the silicon wafer, insulating oxide, intrinsic polysilicon, back-gate oxide, and silicon film. Two different approaches have been taken for preparing the SOIAS wafers. The first is the more traditional route of the BESOI process. In this case, the device wafer includes the back-gate oxide (to be) which is obtained by dry thermal oxidation, and the back-gate material to be which is amorphous silicon (as deposited). This device wafer was then bonded to the handle wafer which was also oxidized to form approximately 1 m of silicon dioxide. Therefore, the bonding interface is between the amorphous silicon and the thick insulating oxide. After bonding, the wafers were annealed in N at 1000 C for 1 h. The device wafer was then thinned back by chemical and mechanical polishing. Finally, localized plasma thinning (Accu-Thin)1 was used to improve silicon film uniformity. The second approach involves the bonding of a SIMOX wafer. The buried oxide, in this case, served as an etch-stop using wet chemistry wafer etching. The same layers as described above were grown on the SIMOX and the handle wafers. The bonding interface was still between the amorphous silicon and 1 Accu-Thin is a trademark technology of Hughes. 824 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 5, MAY 1997